VIA's HDIT Architecture
VIA's HDIT Architecture features a high-performance HDIT North Bridge chip with a high-speed DDR266 memory controller interface, AGP 4X, and support for up to four processors. For high-end workstation and server applications, System OEMs can configure the memory interface in HDIT mode and utilize it in conjunction with HDIT Memory Buffers to boost memory bandwidth to rates of up to 4.2GB per second with a 128-bit data path. The data transfer rate from the HDIT North Bridge to the AGP port and I/O expansion slots can also be increased to speeds of up to 2.1GB per second by configuring the system in HDIT mode and integrating two additional 64-bit HDIT PCI-X companion chips.

To ensure a balanced system architecture, VIA is coupling its HDIT North Bridge chip with a new enhanced legacy-free HDIT South Bridge featuring a wide range of integrated functions including dual ATA-100 EIDE controllers, 8-channel HW accelerated Audio and HSP modem, six port USB, integrated networking, and an LPC (Low Pin Count) bus running at 66MHz.

To overcome the bandwidth limitations of the 32-bit, 33MHz PCI bus, the HDIT North Bridge and HDIT South Bridge are connected with the new high-speed V-Link bus that runs in 66MHz or 133MHz modes and delivers data transfer rates of up to 512MB per second.

"The HDIT V-Link is a high efficiency, low latency bus structure with configurable bandwidth ranges to satisfy different segment system I/O requirements," said Eric Chang, Director of Product Marketing for VIA Technologies, Inc. "The 32-bit, 33MHz PCI bus with a peak bandwidth of 133MB/S, is no longer sufficient as the primary bus between the North Bridge and South Bridge and system expansion for advanced PC systems, which are already being equipped with 1GHz processors. Any high-performance system with leading DRAM technology such as DDR SDRAM would be handicapped when paired with a 32-bit/33MHz PCI South Bridge. The system would not be able to fully benefit from advanced DDR SDRAM because the PCI bus has now become the system bottleneck."

The first VIA HDIT chipset is targeted for sampling early in the first half of 2001, and will be implemented for high-end desktop, workstation, and server applications that support leading processors from both Intel and AMD.