Architectural Features of Intel Pentium 4 Processor

A brief overview of the Intel Pentium 4 processor's architectural features, we shall discuss these in more detail later on in our Pentium 4 Architecture section. We have however, decided to publish information sent to us by Intel to our labs team, to ensure you receive the facts as they are published by Intel.

Intel® NetBurst™ Micro-architecture
The NetBurst micro-architecture delivers a number of new and innovative features including (Hyper Pipelined Technology, 400 MHz System Bus, Execution Trace Cache, and Rapid Execution Engine) as well as a number of enhanced features (Advanced Transfer Cache, Advanced Dynamic Execution, Enhanced Floating-point and Multi-media Unit, and Streaming SIMD Extensions 2 (SSE2)). Many of these new innovations and advances were made possible with improvements in processor technology, process technology, and circuit design and could not previously be implemented in high-volume, manufacturability solutions. The features and resulting benefits of the new micro-architecture are defined below: -

Hyper Pipelined Technology
The hyper-pipelined technology of the NetBurst micro-architecture doubles the pipeline depth compared to the P6 micro-architecture used on today's Pentium III processors. One of the key pipelines, the branch prediction / recovery pipeline, is implemented in 20 stages in the NetBurst micro-architecture, compared to 10 stages in the P6 micro-architecture. This technology significantly increases the performance, frequency, and scalability of the processor.

400 MHz System Bus
The Pentium 4 processor supports Intel's highest performance desktop system bus by delivering 3.2 GB of data per second into and out of the processor. This is accomplished through a physical signalling scheme of quad pumping the data transfers over a 100-MHz clocked system bus and a buffering scheme allowing for sustained 400-MHz data transfers. This compares to 1.06 GB/s delivered on the Pentium® III processor's 133-MHz system bus.

Level 1 Execution Trace Cache
In addition to the 8 KB data cache, the Pentium 4 processor includes an Execution Trace Cache that stores up to 12 K decoded micro-ops in the order of program execution. This increases performance by removing the decoder from the main execution loop and makes more efficient usage of the cache storage space since instructions that are branched around are not stored. The result is a means to deliver a high volume of instructions to the processor's execution units and a reduction in the overall time required to recover from branches that have been miss-predicted.

Rapid Execution Engine
Two Arithmetic Logic Units (ALUs) on the Pentium 4 processor are clocked at twice the core processor frequency. This allows basic integer instructions such as Add, Subtract, Logical AND, Logical OR, etc. to execute in ½ a clock cycle. For example, the Rapid Execution Engine on a 1.50 GHz Pentium 4 processor runs at 3 GHz.

256 KB, Level 2 Advanced Transfer Cache
The Level 2 Advanced Transfer Cache (ATC) is 256KB in size and delivers a much higher data throughput channel between the Level 2 cache and the processor core. The Advanced Transfer Cache consists of a 256-bit (32-byte) interface that transfers data on each core clock. As a result, the Pentium 4 processor 1.50 GHz can deliver a data transfer rate of 48 GB/s. This compares to a transfer rate of 16 GB/s on the Pentium® III processor at 1 GHz. Features of the ATC include:

• Non-Blocking, full speed, on-die level 2 cache
• 8-way set associativity
• 256-bit data bus to the level 2 cache
• Data clocked into and out of the cache every clock cycle

Advanced Dynamic Execution
The Advance Dynamic Execution engine is a very deep, out-of-order speculative execution engine that keeps the execution units executing instructions. The Pentium 4 processor can also view 126 instructions in flight and handle up to 48 loads and 24 stores in the pipeline. It also includes an enhanced branch prediction algorithm that has the net effect of reducing the number of branch predictions-predictions by about 33% over the P6 generation processor's branch prediction capability. It does this by implementing a 4 KB branch target buffer that stores more detail on the history of past branches, as well as by implementing a more advanced branch prediction algorithm.

Enhanced Floating-point and Multi-media Unit
The Pentium 4 processor expands the floating-point registers to a full 128-bit and adds an additional register for data movement which improves performance on both floating-point and multi-media applications.

Internet Streaming SIMD Extensions 2 (SSE2)
With the introduction of SSE2, the NetBurst micro-architecture now extends the SIMD capabilities that MMX technology and SSE technology delivered by adding 144 new instructions. These instructions include 128-bit SIMD integer arithmetic and 128-bit SIMD double-precision floating-point operations. These new instructions reduce the overall number of instructions required to execute a particular program task and as a result can contribute to an overall performance increase. They accelerate a broad range of applications, including video, speech, and image, photo processing, encryption, financial, engineering and scientific applications.

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