The Almador Feature Set

Almador will support both the Coppermine-T and Tualatin processors at 133Mhz FSB, with the ability to extend to 200MHz in the future when used with Tualatin processors. Intel is not suggesting that its customers use any other chip set with Tualatin. Almador will support a maximum memory capacity of 1.5Gbytes as compared to the 815 which is limited to 512M. Enough has been said about DDR vs SDR.

There remains one final shocking feature of Almador that has not yet surfaced in the industry rumor mill. The 810 and the 815 both support a small 32-bit 133MHz 4Mbyte SDRAM graphics memory option, which is used for Z-buffer data by the integrated graphics controller. Intel calls this feature a 'Display Cache Controller' or DCC. When this additional SDRAM bus is populated, it can improve the performance of some 3D applications by a small margin, but even with this feature activated, the 810/815 3D performance is still entirely uncompetitive for serious 3D. As a result, few OEMs or board makers are actually populating this extra memory bus. Knowing this, Intel has also defined an external SDRAM module option that will allow an OEM the option add this Display Cache SDRAM for some configurations, without burdening all of its customers.

The amazing news is that in Almador, Intel will be converting this unused bus to RDRAM.

Since Intel's 820+MTH strategy has failed, this may be nothing more than Intel's last-ditch effort to ship unpopulated RDRAM interfaces, so that Intel can satisfy the 20% unit volume clause of its contract with Rambus.

Since Intel's 820+MTH strategy has failed, this single attribute of Almador may be nothing more than Intel's last-ditch effort to ship unpopulated RDRAM interfaces, so that Intel can satisfy the 20% unit volume clause of its contract with Rambus.

Will the attach rate of RDRAM as a Display Cache memory be higher than it has been for SDRAM? On the surface it does not seem likely. Will RDRAM finally give Intel what it needs to make Almador a competitive 3D platform? We don't think that memory bandwidth is Intel's only barrier in this case. The integrated 740-like graphics controller has other feature set and performance shortcomings that cannot be masked by RDRAM alone. Intel's roadmap seems to support this analysis, considering that Almador is positioned even below the 815. We believe that Intel realizes that the Display Cache interface, (SDRAM or RDRAM) is even less likely to be used in the future than it is today.

Intel is also rumored to be hard at work developing a special memory module for this application, referred to as a Media-RIMM or M-RIMM using today's standard 128Mbit RDRAM chips. This means that the minimum configuration for this memory module will be 16Mbytes. For use only as a Z-buffer, 16MB of high bandwidth RDRAM is massive overkill. Intel could have the option to change its DCC design to move all graphics memory operations to this display cache buffer. This could be an interesting strategy, but we still believe that the product will be constrained by the features and performance of the controller.

Cost will certainly be another factor. Considering the RDRAM cost premium alone, a 16MB M-RIMM might be nearly as expensive as a low cost mainstream 3D AGP accelerator from nVidia or ATI. Any user that is truly interested in 3D might perceive that his money is better spent in an external feature-rich AGP card. Assuming that its new Display Cache feature is not popularly used, and that Tualatin ships with a 133MHz FSB, it is difficult to see what Almador will bring to the table that the 815/815E cannot. Here, Intel has left itself vulnerable to competition from third party DDR UMA that will be released prior to Almador.

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